Implementation of Low Power DFT for ASIC SOC

Abstract

In System on Chip (SoC), a low power DFT technique plays a crucial role to reduce power consumption. These low power techniques throw a major challenge for the designers and verification engineers. Different low power DFT techniques like multiple Supply Voltages, Power Switches, clock gating, low power isolation cells and so on are applied at various stages of DFT flow. In this brief, the primary focus is to reduce the dynamic power consumption of a digital circuit in the scan Synthesis phase. Here a common clock is connected to all scan flip-flops with a frequency of 40MHz.Without any timing violations, the clock frequency is reduced to 20MHz thereby ensuring that there is a reduction in dynamic power consumption to a value of 50%.