Performance Analysis of High Speed and Area Efficient Finite Impulse Response Filters

  • Md. Zakir Hussain Assistant Professor, ECED, Muffakham Jah College of Engineering and Technology, Hyderabad, India
  • Kazi Nikhat Parvin Assistant Professor, ECED, Bhoj Reddy Engineering College for Women, Hyderabad, India
Keywords: Digital filters, Finite impulse response (FIR), FPGA.

Abstract

This study represents the designing and implementation of a bandpass finite impulse response (FIR) filter of order 31 using windowing techniques. The frequency parameters used are of a typical GSM receiver,19 which is one of the applications of software-defined radio (SDR). To minimize filter area, various multiplication techniques like a canonical signed digit, Vedic multiplier, booth multiplier, and modified booth multiplier are used. Adders like ripple carry adder, carry save adder, carry look ahead adder, and Kogge-Stone adder are used to add the product from the multiplier unit. A comparison between three different windows has been made. The FIR is designed in MATLAB using a windowing technique. Then it is synthesized on Xilinx 14.7, Virtex 6 XC6VLX760, whose results are included in this paper.

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Published
2020-06-30